[ros-diffs] [sir_richard] 49757: [FREELDR]: Fix RAM layout assumptions in ARM code.

sir_richard at svn.reactos.org sir_richard at svn.reactos.org
Tue Nov 23 17:54:12 UTC 2010


Author: sir_richard
Date: Tue Nov 23 17:54:11 2010
New Revision: 49757

URL: http://svn.reactos.org/svn/reactos?rev=49757&view=rev
Log:
[FREELDR]: Fix RAM layout assumptions in ARM code.

Modified:
    trunk/reactos/boot/freeldr/freeldr/windows/arm/wlmemory.c

Modified: trunk/reactos/boot/freeldr/freeldr/windows/arm/wlmemory.c
URL: http://svn.reactos.org/svn/reactos/trunk/reactos/boot/freeldr/freeldr/windows/arm/wlmemory.c?rev=49757&r1=49756&r2=49757&view=diff
==============================================================================
--- trunk/reactos/boot/freeldr/freeldr/windows/arm/wlmemory.c [iso-8859-1] (original)
+++ trunk/reactos/boot/freeldr/freeldr/windows/arm/wlmemory.c [iso-8859-1] Tue Nov 23 17:54:11 2010
@@ -19,16 +19,31 @@
 #define PTE_BASE                    0xC0000000
 #define PDE_BASE                    0xC0400000
 #define PDR_BASE                    0xFFD00000
+#define VECTOR_BASE                 0xFFFF0000
+
+#ifdef _ZOOM2_
+#define IDMAP_BASE                  0x81000000
 #define MMIO_BASE                   0x10000000
-#define VECTOR_BASE                 0xFFFF0000
-
-#define LowMemPageTableIndex        0
+#else
+#define IDMAP_BASE                  0x00000000
+#define MMIO_BASE                   0x10000000
+#endif
+
+#define LowMemPageTableIndex        (IDMAP_BASE >> PDE_SHIFT)
+#define MmioPageTableIndex          (MMIO_BASE >> PDE_SHIFT)
 #define KernelPageTableIndex        (KSEG0_BASE >> PDE_SHIFT)
 #define StartupPtePageTableIndex    (PTE_BASE >> PDE_SHIFT)
 #define StartupPdePageTableIndex    (PDE_BASE >> PDE_SHIFT)
-#define MmioPageTableIndex          (MMIO_BASE >> PDE_SHIFT)
 #define PdrPageTableIndex           (PDR_BASE >> PDE_SHIFT)
 #define VectorPageTableIndex        (VECTOR_BASE >> PDE_SHIFT)
+
+#ifndef _ZOOM2_
+PVOID MempPdrBaseAddress = (PVOID)0x70000;
+PVOID MempKernelBaseAddress = (PVOID)0;
+#else
+PVOID MempPdrBaseAddress = (PVOID)0x81100000;
+PVOID MempKernelBaseAddress = (PVOID)0x80000000;
+#endif
 
 /* Converts a Physical Address into a Page Frame Number */
 #define PaToPfn(p)                  ((p) >> PFN_SHIFT)
@@ -188,15 +203,18 @@
     TempPte.Accessed = TempPte.Valid = TempLargePte.LargePage = TempLargePte.Accessed = TempPde.Valid = 1;
 
     /* Allocate the 1MB "PDR" (Processor Data Region). Must be 1MB aligned */
-    PdrPage = MmAllocateMemoryAtAddress(sizeof(KPDR_PAGE), (PVOID)0x700000, LoaderMemoryData);
+    PdrPage = MmAllocateMemoryAtAddress(sizeof(KPDR_PAGE),
+                                        MempPdrBaseAddress,
+                                        LoaderMemoryData);
 
     /* Setup the Low Memory PDE as an identity-mapped Large Page (1MB) */
     LargePte = &PdrPage->PageDir.Pte[LowMemPageTableIndex];
+    TempLargePte.PageFrameNumber = PaToLargePfn(IDMAP_BASE);
     *LargePte = TempLargePte;
 
     /* Setup the MMIO PDE as two identity mapped large pages -- the kernel will blow these away later */
     LargePte = &PdrPage->PageDir.Pte[MmioPageTableIndex];
-    Pfn = PaToLargePfn(0x10000000);
+    Pfn = PaToLargePfn(MMIO_BASE);
     for (i = 0; i < 2; i++)
     {
         TempLargePte.PageFrameNumber = Pfn++;
@@ -215,13 +233,13 @@
 
     /* Setup the Kernel PTEs */
     PointerPte = PdrPage->KernelPageTable[0].Pte;
-    Pfn = 0;
+    Pfn = PaPtrToPfn(MempKernelBaseAddress);
     for (i = 0; i < 3072; i++)
     {
         TempPte.PageFrameNumber = Pfn++;
         *PointerPte++ = TempPte;
     }
-    
+
     /* Done */
     return TRUE;
 }




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