[ros-diffs] [akhaldi] 47258: [NTOSKRNL] - Add KiGetSecondLevelDCacheSize (for all the available architectures) and MiGetPdeOffset macros. - Remove conflicting PDE_SIZE definitions (both aren't used anywhere). - Fix ValidKernelPde, PointerPte and PointerPde types and correct their use (mminit.c). - Thanks to the work that was done over the recent commits (in the header branch) and this one, the kernel now builds (but doesn't link yet) for ARM.
akhaldi at svn.reactos.org
akhaldi at svn.reactos.org
Mon May 17 23:26:51 CEST 2010
Author: akhaldi
Date: Mon May 17 23:26:51 2010
New Revision: 47258
URL: http://svn.reactos.org/svn/reactos?rev=47258&view=rev
Log:
[NTOSKRNL]
- Add KiGetSecondLevelDCacheSize (for all the available architectures) and MiGetPdeOffset macros.
- Remove conflicting PDE_SIZE definitions (both aren't used anywhere).
- Fix ValidKernelPde, PointerPte and PointerPde types and correct their use (mminit.c).
- Thanks to the work that was done over the recent commits (in the header branch) and this one, the kernel now builds (but doesn't link yet) for ARM.
Modified:
branches/header-work/ntoskrnl/include/internal/amd64/ke.h
branches/header-work/ntoskrnl/include/internal/amd64/mm.h
branches/header-work/ntoskrnl/include/internal/arm/ke.h
branches/header-work/ntoskrnl/include/internal/arm/mm.h
branches/header-work/ntoskrnl/include/internal/i386/ke.h
branches/header-work/ntoskrnl/include/internal/i386/mm.h
branches/header-work/ntoskrnl/include/internal/powerpc/ke.h
branches/header-work/ntoskrnl/mm/ARM3/miarm.h
branches/header-work/ntoskrnl/mm/ARM3/mminit.c
Modified: branches/header-work/ntoskrnl/include/internal/amd64/ke.h
URL: http://svn.reactos.org/svn/reactos/branches/header-work/ntoskrnl/include/internal/amd64/ke.h?rev=47258&r1=47257&r2=47258&view=diff
==============================================================================
--- branches/header-work/ntoskrnl/include/internal/amd64/ke.h [iso-8859-1] (original)
+++ branches/header-work/ntoskrnl/include/internal/amd64/ke.h [iso-8859-1] Mon May 17 23:26:51 2010
@@ -115,6 +115,12 @@
//
#define KeGetContextSwitches(Prcb) \
(Prcb->KeContextSwitches)
+
+//
+// Macro to get the second level cache size field name which differs between
+// CISC and RISC architectures, as the former has unified I/D cache
+//
+#define KiGetSecondLevelDCacheSize() ((PKIPCR)KeGetPcr())->SecondLevelCacheSize
#define KeGetExceptionFrame(Thread) \
(PKEXCEPTION_FRAME)((ULONG_PTR)KeGetTrapFrame(Thread) - \
Modified: branches/header-work/ntoskrnl/include/internal/amd64/mm.h
URL: http://svn.reactos.org/svn/reactos/branches/header-work/ntoskrnl/include/internal/amd64/mm.h?rev=47258&r1=47257&r2=47258&view=diff
==============================================================================
--- branches/header-work/ntoskrnl/include/internal/amd64/mm.h [iso-8859-1] (original)
+++ branches/header-work/ntoskrnl/include/internal/amd64/mm.h [iso-8859-1] Mon May 17 23:26:51 2010
@@ -112,6 +112,8 @@
#define ADDR_TO_PDE_OFFSET(v) ((((ULONG_PTR)(v)) / (512 * PAGE_SIZE)))
#define ADDR_TO_PTE_OFFSET(v) ((((ULONG_PTR)(v)) % (512 * PAGE_SIZE)) / PAGE_SIZE)
+#define MiGetPdeOffset ADDR_TO_PDE_OFFSET
+
#define VAtoPXI(va) ((((ULONG64)va) >> PXI_SHIFT) & 0x1FF)
#define VAtoPPI(va) ((((ULONG64)va) >> PPI_SHIFT) & 0x1FF)
#define VAtoPDI(va) ((((ULONG64)va) >> PDI_SHIFT) & 0x1FF)
Modified: branches/header-work/ntoskrnl/include/internal/arm/ke.h
URL: http://svn.reactos.org/svn/reactos/branches/header-work/ntoskrnl/include/internal/arm/ke.h?rev=47258&r1=47257&r2=47258&view=diff
==============================================================================
--- branches/header-work/ntoskrnl/include/internal/arm/ke.h [iso-8859-1] (original)
+++ branches/header-work/ntoskrnl/include/internal/arm/ke.h [iso-8859-1] Mon May 17 23:26:51 2010
@@ -54,6 +54,12 @@
//
#define KeGetContextSwitches(Prcb) \
CONTAINING_RECORD(Prcb, KIPCR, PrcbData)->ContextSwitches
+
+//
+// Macro to get the second level cache size field name which differs between
+// CISC and RISC architectures, as the former has unified I/D cache
+//
+#define KiGetSecondLevelDCacheSize() ((PKIPCR)KeGetPcr())->SecondLevelDcacheSize
//
// Returns the Interrupt State from a Trap Frame.
Modified: branches/header-work/ntoskrnl/include/internal/arm/mm.h
URL: http://svn.reactos.org/svn/reactos/branches/header-work/ntoskrnl/include/internal/arm/mm.h?rev=47258&r1=47257&r2=47258&view=diff
==============================================================================
--- branches/header-work/ntoskrnl/include/internal/arm/mm.h [iso-8859-1] (original)
+++ branches/header-work/ntoskrnl/include/internal/arm/mm.h [iso-8859-1] Mon May 17 23:26:51 2010
@@ -1,10 +1,6 @@
#pragma once
-//
-// Number of bits corresponding to the area that a PDE entry represents (1MB)
-//
#define PDE_SHIFT 20
-#define PDE_SIZE (1 << PDE_SHIFT)
//
// Number of bits corresponding to the area that a coarse page table entry represents (4KB)
Modified: branches/header-work/ntoskrnl/include/internal/i386/ke.h
URL: http://svn.reactos.org/svn/reactos/branches/header-work/ntoskrnl/include/internal/i386/ke.h?rev=47258&r1=47257&r2=47258&view=diff
==============================================================================
--- branches/header-work/ntoskrnl/include/internal/i386/ke.h [iso-8859-1] (original)
+++ branches/header-work/ntoskrnl/include/internal/i386/ke.h [iso-8859-1] Mon May 17 23:26:51 2010
@@ -58,6 +58,12 @@
//
#define KeGetContextSwitches(Prcb) \
CONTAINING_RECORD(Prcb, KIPCR, PrcbData)->ContextSwitches
+
+//
+// Macro to get the second level cache size field name which differs between
+// CISC and RISC architectures, as the former has unified I/D cache
+//
+#define KiGetSecondLevelDCacheSize() ((PKIPCR)KeGetPcr())->SecondLevelCacheSize
//
// Returns the Interrupt State from a Trap Frame.
Modified: branches/header-work/ntoskrnl/include/internal/i386/mm.h
URL: http://svn.reactos.org/svn/reactos/branches/header-work/ntoskrnl/include/internal/i386/mm.h?rev=47258&r1=47257&r2=47258&view=diff
==============================================================================
--- branches/header-work/ntoskrnl/include/internal/i386/mm.h [iso-8859-1] (original)
+++ branches/header-work/ntoskrnl/include/internal/i386/mm.h [iso-8859-1] Mon May 17 23:26:51 2010
@@ -35,6 +35,8 @@
#define ADDR_TO_PAGE_TABLE(v) (((ULONG)(v)) / (1024 * PAGE_SIZE))
#define ADDR_TO_PDE_OFFSET(v) ((((ULONG)(v)) / (1024 * PAGE_SIZE)))
#define ADDR_TO_PTE_OFFSET(v) ((((ULONG)(v)) % (1024 * PAGE_SIZE)) / PAGE_SIZE)
+
+#define MiGetPdeOffset ADDR_TO_PDE_OFFSET
/* Easy accessing PFN in PTE */
#define PFN_FROM_PTE(v) ((v)->u.Hard.PageFrameNumber)
Modified: branches/header-work/ntoskrnl/include/internal/powerpc/ke.h
URL: http://svn.reactos.org/svn/reactos/branches/header-work/ntoskrnl/include/internal/powerpc/ke.h?rev=47258&r1=47257&r2=47258&view=diff
==============================================================================
--- branches/header-work/ntoskrnl/include/internal/powerpc/ke.h [iso-8859-1] (original)
+++ branches/header-work/ntoskrnl/include/internal/powerpc/ke.h [iso-8859-1] Mon May 17 23:26:51 2010
@@ -40,6 +40,12 @@
//#define KD_BREAKPOINT_TYPE
//#define KD_BREAKPOINT_SIZE
//#define KD_BREAKPOINT_VALUE
+
+//
+// Macro to get the second level cache size field name which differs between
+// CISC and RISC architectures, as the former has unified I/D cache
+//
+#define KiGetSecondLevelDCacheSize() ((PKIPCR)KeGetPcr())->SecondLevelDcacheSize
//
// Macros for getting and setting special purpose registers in portable code
Modified: branches/header-work/ntoskrnl/mm/ARM3/miarm.h
URL: http://svn.reactos.org/svn/reactos/branches/header-work/ntoskrnl/mm/ARM3/miarm.h?rev=47258&r1=47257&r2=47258&view=diff
==============================================================================
--- branches/header-work/ntoskrnl/mm/ARM3/miarm.h [iso-8859-1] (original)
+++ branches/header-work/ntoskrnl/mm/ARM3/miarm.h [iso-8859-1] Mon May 17 23:26:51 2010
@@ -42,8 +42,7 @@
#define _1KB (1024)
#define _1MB (1024 * _1KB)
-/* Size of a PDE directory, and size of a page table */
-#define PDE_SIZE (PDE_COUNT * sizeof(MMPDE))
+/* Size of a page table */
#define PT_SIZE (PTE_COUNT * sizeof(MMPTE))
/* Architecture specific count of PDEs in a directory, and count of PTEs in a PT */
@@ -169,7 +168,7 @@
} MMCOLOR_TABLES, *PMMCOLOR_TABLES;
extern MMPTE HyperTemplatePte;
-extern MMPTE ValidKernelPde;
+extern MMPDE ValidKernelPde;
extern MMPTE ValidKernelPte;
extern ULONG MmSizeOfNonPagedPoolInBytes;
Modified: branches/header-work/ntoskrnl/mm/ARM3/mminit.c
URL: http://svn.reactos.org/svn/reactos/branches/header-work/ntoskrnl/mm/ARM3/mminit.c?rev=47258&r1=47257&r2=47258&view=diff
==============================================================================
--- branches/header-work/ntoskrnl/mm/ARM3/mminit.c [iso-8859-1] (original)
+++ branches/header-work/ntoskrnl/mm/ARM3/mminit.c [iso-8859-1] Mon May 17 23:26:51 2010
@@ -314,13 +314,13 @@
//
// Puerile piece of junk-grade carbonized horseshit puss sold to the lowest bidder
//
- ULONG Pde = ADDR_TO_PDE_OFFSET(AddressStart);
- while (Pde <= ADDR_TO_PDE_OFFSET(AddressEnd))
+ ULONG Pde = MiGetPdeOffset(AddressStart);
+ while (Pde <= MiGetPdeOffset(AddressEnd))
{
//
// This both odious and heinous
//
- extern ULONG MmGlobalKernelPageDirectory[1024];
+ extern ULONG MmGlobalKernelPageDirectory[];
MmGlobalKernelPageDirectory[Pde] = ((PULONG)PDE_BASE)[Pde];
Pde++;
}
@@ -360,10 +360,10 @@
if (!MmSecondaryColors)
{
/* Get L2 cache information */
- L2Associativity = KeGetPcr()->SecondLevelCacheAssociativity;
+ L2Associativity = KiGetSecondLevelDCacheSize();
/* The number of colors is the number of cache bytes by set/way */
- MmSecondaryColors = KeGetPcr()->SecondLevelCacheSize;
+ MmSecondaryColors = KiGetSecondLevelDCacheSize();
if (L2Associativity) MmSecondaryColors /= L2Associativity;
}
@@ -681,7 +681,7 @@
/* Yes we do, set it up */
Pfn1 = MI_PFN_TO_PFNENTRY(PageFrameIndex);
Pfn1->u4.PteFrame = StartupPdIndex;
- Pfn1->PteAddress = PointerPde;
+ Pfn1->PteAddress = (PMMPTE)PointerPde;
Pfn1->u2.ShareCount++;
Pfn1->u3.e2.ReferenceCount = 1;
Pfn1->u3.e1.PageLocation = ActiveAndValid;
@@ -764,7 +764,7 @@
/* Make it a bogus page to catch errors */
PointerPde = MiAddressToPde(0xFFFFFFFF);
Pfn1->u4.PteFrame = PFN_FROM_PTE(PointerPde);
- Pfn1->PteAddress = PointerPde;
+ Pfn1->PteAddress = (PMMPTE)PointerPde;
Pfn1->u2.ShareCount++;
Pfn1->u3.e2.ReferenceCount = 0xFFF0;
Pfn1->u3.e1.PageLocation = ActiveAndValid;
@@ -1404,8 +1404,10 @@
NTAPI
MiBuildPagedPool(VOID)
{
- PMMPTE PointerPte, PointerPde;
+ PMMPTE PointerPte;
+ PMMPDE PointerPde;
MMPTE TempPte = ValidKernelPte;
+ MMPDE TempPde = ValidKernelPde;
PFN_NUMBER PageFrameIndex;
KIRQL OldIrql;
ULONG Size, BitMapSize;
@@ -1506,10 +1508,10 @@
// Allocate a page and map the first paged pool PDE
//
PageFrameIndex = MmAllocPage(MC_NPPOOL);
- TempPte.u.Hard.PageFrameNumber = PageFrameIndex;
+ TempPde.u.Hard.PageFrameNumber = PageFrameIndex;
ASSERT(PointerPde->u.Hard.Valid == 0);
- ASSERT(TempPte.u.Hard.Valid == 1);
- *PointerPde = TempPte;
+ ASSERT(TempPde.u.Hard.Valid == 1);
+ *PointerPde = TempPde;
//
// Release the PFN database lock
@@ -1521,7 +1523,7 @@
// will be allocated to handle paged pool growth. This is where they'll have
// to start.
//
- MmPagedPoolInfo.NextPdeForPagedPoolExpansion = PointerPde + 1;
+ MmPagedPoolInfo.NextPdeForPagedPoolExpansion = (PMMPTE)(PointerPde + 1);
//
// We keep track of each page via a bit, so check how big the bitmap will
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